1. Field of the Invention
The present invention relates to a duplexed processor system and, in particular, to a duplexed processor system whose each processor card is equipped with a plurality of processor units.
2. Description of the Related Art
Generally, in a duplexed processor system configured to attain high availability of communications equipment and the like, a processor card equipped with a high-speed processor is separated from an input/output unit, and active- and standby-system processors are connected by buses and the like, so that respective memory contents of the active- and standby-system processors agree with each other. In recent years, it has been required that such a duplexed processor system be enhanced in processor performance, reliability of communications mechanism between mates, function of one card and space factor.
In order to meet such requirements, a duplexed processor system has been disclosed in, for example, “NODE CONTROL PROCESSOR (Denshi Tsushin Gakkai, 2001 Society Taikai, B-6-74)”, in which built-in high-speed processors are equipped, a communications mechanism between mates is enabled by serial links added with ECC (error correction codes), and cross interfaces to input/output cards are provided.
The configuration of the duplexed processor system disclosed in the above literature is shown in FIG. 1. In FIG. 1, reference characters CP0 and CP1 are central processing units; reference characters MC0 and MC1 are other system processor connection units; reference characters MM0 and MM1 are main memories; reference characters B00, B01, B10, and B11 are bus interface units; and reference characters FM0 and FM1 are input/output interface units. Each respective processor unit of 0- and 1-system processor cards C0 and C1 comprises the central processing unit, the other system processor connection unit, and the main memory. The other system processor connection units MC0 and MC1 transfer data between the 0- and 1-system processor units, so that respective contents of the memories MM0 and MM1 agree with each other. The data transfer uses the ECC to cope with an occurrence of data error, and to thereby prevent disagreement between the contents of the memories MM0 and MM1.
Also, the input/output unit of the system is redundantly duplexed by a cross bus BS0 connecting the 0-system processor card C0 and input/output card C3 and by a cross bus BS1 connecting the 1-system processor card C1 and input/output card C2.
However, there is the drawback that, in the communications between mates (i.e. the communications between the 0- and 1-system processor units), an occurrence of data error uncorrectable by ECC causes other system disconnection, simplex running operation, and availability reduction. Also, there is the drawback that, as shown in FIG. 1, configuring the duplexed processor system requires at least four cards, which has difficulty in the application to space-saving equipment.
Also, there is the drawback that in the case of the execution of application software requiring processor power, each processor card equipped with one processor causes incomplete computation within a fixed time, which consequently cannot assure operation as communications equipment to which the duplexed processor system is applied. This drawback may be overcome by employing a duplexed multiprocessor system as the duplexed processor system. For example, in the case of the employment of a duplexed multiprocessor system whose each processor card is equipped with a plurality of processor units each comprising a CPU, an other system processor connection unit, and a main memory, the communications between the processor units on the same card are required so as to reduce the load of each processor unit, thereby enhancing system performance.